Data processing systems sometimes incorporate data coherency protocols to coordinate data operations between different subsystems. A multi-processor data processing system (an MP system) is a system that uses such a data coherency protocol. In an MP system, each data processor in a group of data processors stores a subset of the system's memory in an associated one of a group of memory caches. The data processors periodically load data from the system's main memory system into the associated memory cache and vice versa. Each data processor can modify the data in its memory cache independent of every other data processor. Without some coherency scheme, the data stored in the common memory subsystem would become hopelessly confused as each data processor modified its subset of the memory without consideration of every other data processor's actions.
Cache memory systems are only one example of devices that use data coherency protocols. Generally, any system that can store the same data in two or more locations can benefit from a data coherency protocol. The "data" need not be stored in a memory cache. For instance, the data could describe the translation of a particular group of virtual addresses to a corresponding group of effective addresses. This type of data is typically stored in a special purpose table within each data processor.
A memory coherency scheme defines a set of data states and 'set of data operations that modify the data states in a predetermined order. Each memory byte, half-word, word, etc. is assigned a state and data describing the state accompanies the data when ever it is loaded into or out of a memory system. Typically, the states define what fights a particular data processor has with the respect to the data and whether or not the data itself is valid. These rights may include or exclude the data processor's fight to modify the data. Each data processor broadcasts any operation that could modify the state of a piece of data. The broadcast contains information identifying the data and the operation the data processor intends to perform on the data. Conversely, each of the other data processors monitors these broadcasts for operations that might change the state of data stored in each of the other data processors. This procedure is known as "snooping." The other data processors can then modify their relevant data states when necessary or assert a signal temporarily suspending a broadcast operation pending some requisite operation.
A data processor must query each of its coherent memories each time it snoops a data operation. As described above, these coherent memories may be cache memory subsystems, specialized tables or input and output queues to either the cache memory subsystems or the specialized tables. These coherent memories will respond to the data processor indicating whether they contain a copy of the snooped data and the data state associated with the data. However, sometimes the coherent memory systems are unable to answer the query in the time allotted them. In this case, the data processor will assert a response forcing the broadcasting data processor to retry the operation at a later time when the data processors will re-query their coherent memories. Bus bandwidth is degraded when a snooping data processor forces another data processor to rebroadcast a data operation at a later time. Therefore, the number of false rebroadcast signals should be minimized.